This set of Important Addressing Modes MCQ Questions covers advanced concepts of Computer Organization and Architecture (COA) including PC-Relative Addressing, Based-Indexed Addressing, Memory Indirect Addressing, RISC Addressing Modes, and complex effective address calculations. These questions are highly useful for GATE, IBPS IT Officer, university semester exams, and technical interview preparation.
Topic: Instruction Set Architecture & Addressing Modes | Set: 3
Difficulty: Hard |Total Questions: 15
Important Addressing Modes MCQ Questions
Q1: In a system with Multi-level Indirection, if the pointer bit is ‘1’, the CPU:
A. Fetches the operand
B. Fetches another address
C. Aborts the instruction
D. Increments the PC
View Answer & Explanation
Answer: B
Explanation: It continues following the chain of pointers until a pointer bit of ‘0’ is encountered.
Q2: Which addressing mode minimizes the instruction length while still allowing access to a large memory?
A. Register Indirect
B. Direct
C. Immediate
D. Absolute
View Answer & Explanation
Answer: A
Explanation: Only a few bits are needed to name a register, which then points to a full memory address.
Q3: In the PowerPC architecture, “Update” addressing is similar to:
A. Immediate
B. Auto-increment
C. PC-Relative
D. Direct
View Answer & Explanation
Answer: B
Explanation: Update mode modifies the base register during instruction execution similar to auto-increment mode.
Q4: How many memory accesses occur during the instruction cycle of a Memory Indirect instruction?
A. 1
B. 2
C. 3
D. 4
View Answer & Explanation
Answer: C
Explanation: One access fetches the instruction, another fetches the pointer, and the final access retrieves the operand.
Q5: For a branch instruction at address 500, if the displacement is -50 in PC-Relative mode, the target is:
A. 550
B. 450
C. 451
D. 500
View Answer & Explanation
Answer: B
Explanation: Effective Address = PC + Displacement = 500 + (-50) = 450.
Q6: Which mode is best suited for implementing “Switch-Case” statements or Jump Tables?
A. Direct
B. Indexed Indirect
C. Immediate
D. Register
View Answer & Explanation
Answer: B
Explanation: Indexed indirect mode efficiently accesses jump table entries using base and index calculations.
Q7: In an 8085 microprocessor, the ‘HL’ pair used for memory access represents which mode?
A. Direct
B. Register Indirect
C. Immediate
D. Indexed
View Answer & Explanation
Answer: B
Explanation: The HL register pair acts as a pointer containing the memory address of the operand.
Q8: A CPU uses 32-bit instructions and 32-bit memory addresses. If it supports 128 registers, how many bits are left for the opcode in a 3-register instruction?
A. 11 bits
B. 21 bits
C. 7 bits
D. 25 bits
View Answer & Explanation
Answer: A
Explanation: 128 registers require 7 bits each. Thus, opcode bits = 32 − (3 × 7) = 11 bits.
Q9: In Effective Address calculations for Indexed mode, the index register usually holds:
A. The base address
B. The offset/subscript
C. The instruction
D. The result
View Answer & Explanation
Answer: B
Explanation: The index register stores the offset used to navigate through arrays or data structures.
Q10: Which of the following is true for RISC architectures regarding addressing modes?
A. They have many complex modes
B. They favor simple modes (Register, Immediate)
C. They do not use registers
D. They rely exclusively on Indirect addressing
View Answer & Explanation
Answer: B
Explanation: RISC architectures simplify hardware by using fewer and simpler addressing modes.
Q11: The mode where EA = (PC) + 1 + offset is called:
A. Absolute
B. Relative
C. Indirect
D. Displacement
View Answer & Explanation
Answer: B
Explanation: Relative addressing computes the target address relative to the Program Counter.
Q12: Which mode is used for “Self-Relative” addressing?
A. Based
B. PC-Relative
C. Indexed
D. Direct
View Answer & Explanation
Answer: B
Explanation: Self-relative addressing is another name for PC-relative addressing.
Q13: In “Literal” addressing, the value is:
A. In a register
B. In the next memory word after the opcode
C. In the accumulator
D. Hardcoded in the ALU
View Answer & Explanation
Answer: B
Explanation: Literal addressing stores the operand in the memory location immediately after the instruction.
Q14: What is the primary purpose of the “Post-indexing” mode?
A. To increment the index before use
B. To use the index after an indirect address has been fetched
C. To delete the index after use
D. To speed up the ALU
View Answer & Explanation
Answer: B
Explanation: Post-indexing first fetches the address indirectly and then applies the index offset.
Q15: If an instruction specifies a “Base” register and an “Index” register, it is using:
A. Single Displacement
B. Double Displacement
C. Based-Indexed Addressing
D. Multi-level Indirection
View Answer & Explanation
Answer: C
Explanation: Based-indexed addressing combines a base register and an index register for flexible memory access.
Conclusion
These advanced Addressing Modes MCQ Questions help strengthen understanding of effective address calculation, indirect addressing, indexed addressing, PC-relative addressing, RISC instruction design, and complex instruction execution concepts in Computer Organization and Architecture (COA). Practicing these problems is highly useful for GATE, IBPS IT Officer, technical interviews, and university semester examinations.
Fore theory and concepts, refer to Addressing Modes in Computer Organization.