This set of Addressing Modes MCQ Questions focuses on advanced concepts of Computer Organization and Architecture (COA) including Register Indirect Addressing, Frame Pointer Relative Addressing, Pre-indexing, Post-indexing, Scalable Indexed Addressing, and performance-oriented addressing techniques used in modern processors. These questions are useful for GATE, IBPS IT Officer, university semester exams, and technical interview preparation.
Topic: Instruction Set Architecture & Addressing Modes | Set: 4
Difficulty: Hard to Medium | Total Questions: 15
Important Addressing Modes MCQ Questions
Q1: Which mode provides the fastest access to an operand?
A. Immediate
B. Register
C. Direct
D. Indirect
View Answer & Explanation
Answer: A
Explanation: Immediate addressing fetches the operand directly along with the instruction itself, eliminating additional memory access.
Q2: Which mode is characterized by EA = Reg[R1]?
A. Register Indirect
B. Register
C. Displacement
D. Indexed
View Answer & Explanation
Answer: A
Explanation: Register Indirect addressing uses the contents of a register as the memory address.
Q3: To reduce the “Memory Wall” effect, designers prefer:
A. More Indirect Addressing
B. More Register Addressing
C. Smaller Caches
D. More Direct Addressing
View Answer & Explanation
Answer: B
Explanation: Using registers minimizes slow memory accesses and improves CPU performance.
Q4: Which mode is most commonly used for local variables stored on the stack?
A. PC-Relative
B. Base-Pointer Relative
C. Immediate
D. Direct
View Answer & Explanation
Answer: B
Explanation: Stack frames use a Base Pointer with offsets to efficiently access local variables.
Q5: How many memory references are required for a Register Indirect instruction?
A. 0
B. 1
C. 2
D. 3
View Answer & Explanation
Answer: B
Explanation: One memory access is needed to retrieve the operand from the address stored inside the register.
Q6: A ‘Short’ or ‘Page’ addressing mode uses:
A. Only 8 bits of an address to save space
B. Only 64-bit addresses
C. No addresses
D. Only registers
View Answer & Explanation
Answer: A
Explanation: Page addressing assumes higher-order bits remain fixed, reducing instruction size.
Q7: Which addressing mode is essentially “addressing without an address”?
A. Immediate
B. Implied
C. Direct
D. Indirect
View Answer & Explanation
Answer: B
Explanation: Implied addressing has no explicit address field because the operand is predefined.
Q8: Which mode is most likely used in a JUMP 1000 instruction?
A. Relative
B. Immediate
C. Direct
D. Register Indirect
View Answer & Explanation
Answer: C
Explanation: Direct addressing specifies the exact target memory location explicitly.
Q9: The ‘Scalable’ Indexed mode multiplies the index by:
A. 2, 4, or 8
B. The PC value
C. The Tag bit
D. The Offset
View Answer & Explanation
Answer: A
Explanation: Scaling allows efficient access to arrays of larger data types like integers and doubles.
Q10: Which mode results in the most compact code?
A. Register
B. Indirect
C. Direct
D. Immediate
View Answer & Explanation
Answer: A
Explanation: Register addressing uses very small register identifiers, reducing instruction size.
Q11: In ‘Pre-indexing’, the index is added to the base address:
A. Before the indirect access
B. After the indirect access
C. During the write-back phase
D. Instead of a direct access
View Answer & Explanation
Answer: A
Explanation: Pre-indexing computes the effective address before memory access occurs.
Q12: Which addressing mode is rarely used in modern RISC processors?
A. Memory Indirect
B. Immediate
C. Register
D. PC-Relative
View Answer & Explanation
Answer: A
Explanation: Memory indirect addressing is slower and introduces pipeline complexity in RISC architectures.
Q13: In Direct mode, if the address field is 16 bits and the memory is byte-addressable, the range is:
A. 32 KB
B. 64 KB
C. 128 KB
D. 1 MB
View Answer & Explanation
Answer: B
Explanation: A 16-bit address can represent 216 = 65536 bytes = 64 KB.
Q14: Which mode is used for the destination in STR R1, [R2, #4]?
A. Indirect
B. Displacement (Register Indirect with Offset)
C. Relative
D. Immediate
View Answer & Explanation
Answer: B
Explanation: The effective address is calculated by adding an offset to the base register value.
Q15: The “Address Space” accessible by the CPU is determined by:
A. The number of registers
B. The width of the address bus
C. The number of addressing modes
D. The clock speed
View Answer & Explanation
Answer: B
Explanation: The width of the address bus determines the total number of memory addresses the CPU can access.
Conclusion
These important Addressing Modes MCQ Questions strengthen concepts related to register-based memory access, indirect addressing, stack-relative addressing, scalable indexing, and modern processor instruction execution techniques. Practicing these questions is highly useful for GATE, IBPS IT Officer, university semester examinations, and technical interview preparation in Computer Organization and Architecture (COA).
Fore theory and concepts, refer to Addressing Modes in Computer Organization.